Job Description
• Carry out mask layout design and ensure that it meets design rules;
• Verify that the mask layout integrated circuit design is in accordance with schematic design.
Qualifications/Skills Required
• Diploma / BS or above with major in EE related field.
• Knowledge of UNIX(Linux) platforms and Laker layout tools preferred.
• Posses good understanding of Calibra DRC,LVS and LPE verification.
• Experience in Floor planning, Analog Cell-, Block- and Chip layout.
• Should have a deep understanding of RF & analog layout methods (Shielding / Matching) from device physics.
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